In this part a complementary-parallel CS output stage for the active antenna is characterized, below the test circuit of such a stage is shown where also the biasing is presented.
In the circuit the gate bias of the NMOS and PMOS transistors is swept in order to obtain the common-mode and differential mode characteristics of the class AB output stage.
It is important that the output stage can drive the 100 $\Omega$ load, for this we need a output voltage level of 640$mV$ and a current of 3.2 $mA$.
For the dimensions of the NMOS transistor the obtained values of the previous assigment are used these are:
$W_{NMOS}$ = 50um
$L_{NMOS}$ = 180nm
$M_{NMOS}$ = 2
Now to first obtain the approritae dimension of the PMOS transistor we use the tip given in chapter 6 of the book that the width of the PMOS of the stage should be taken 3.5 times larger compared to the NMOS, since the hole mobility is lower than the electron mobility.
$W_{PMOS}$ = 35um
$L_{PMOS}$ = 180nm
$M_{PMOS}$ = 10
Next is the the quiescent bias current of the stage, at zero input signal,the common-mode current equals the quiescent operating current.
First we plot the (differential) output load voltage of the stage.
Here the bias voltage $V_{b}$ is swept between $100mV$ and $1V$.
From this plot we want to obtain a linear transfer characteristics and to fulfill the drive capability.
The result for a bias voltage of 300 $mV$ seems to give a good linear transfer, which means low crossover distortion also the 640 $mV$ requirement is met with this value.
Below the simulation results of the provided test circuit (corresponsing to the circuit given above) is shown, here the common mode output current is plotted againt the input voltage.
For this plot it is important that there is no deadzone present, which leads to more distortion and a reduction in gain.
Again for the 300$mV$ there is no deadzone visible and the drive requirement of 3.2$mA$ is also met, from this figure we see that the quiescent operating current ($V_{in}=0$) is around $1.25mA$.