"Simulation results"

In the following figure, the properties of the different scaled input stages are shown. Like visible, the transistor current and length can be scaled in such a way that the different scaled transistors comply with the requirments.

Step array

Run	$W$	$L$	$I D$
1	9.00e-04	2.74e-06	2.13e-03
2	7.00e-04	3.56e-06	3.25e-03
3	6.00e-04	4.18e-06	4.37e-03
4	4.00e-04	6.36e-06	1.25e-02

This figure gives the optimal value of the noise performance of the input stage. Indeed, the noise floor is below

6.25 \cdot 10^{- 18} \frac{V^{2}}{H z}

, but this value is barely reached. On the other hand, the 1/f (or 1/f^2) noise easily meets the requirements. To give more headroom to the noise floor, different transistor parameters can be chosen. If the length of the transistor is decreased along with the drain current, the 1/f cutoff frequency will shift to a higher cutoff point and the noise floor will move down. Therefore, a transistor with the following parameters is used to give more headroom.

Another advantage of this is that the

C_{i s s}

of the input transistor will decrease in value. When attempting a frequency compenstation with a phantom zero on the input, a smaller

C_{i s s}

will place the added pole further making sure that it is not dominant (or at least further away). The result is that the phantom zero compensation at the input will be more effective than when the capacitance is bigger. The difference in capacitance is as follows:

Since this simulation is done for a single-CS stage, the designed values need to be adjusted if a differential pair is used. Like mentioned, a differential pair will have the same noise characteristics as a CS stage with transistors that are twice as wide and a drain current that is twice as high. This means that the differential pair will have the following parameters:

Go to Assignment-5---Input-stage-design_index

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Last project update: 2022-01-13 18:09:51