Like mentioned in the requirements section, the noise is predominantly caused by the input stage of the amplifier. Since this amplifier will consist of two stages, the first will be investigated for its noise performance. For this amplifier, a differential pair is chosen as an input stage. Even though a differential pair is different from a single CS stage, its noise performance can be derrived from the performance of a single-CS stage.
If a differential pair has transistors with twice the width of a single-CS stage and if the drain current through the differential pair is twice as large as the drain current of a single CS-stage, the noise characteristic of both devices are identical. Therefore, the noise characteristics of a single-CS stage is simulated. When the differential pair is implemented, the width of the transistors will be doubled and the pair will be biased so the drain current is twice as large as the noise performance results will give. The following figure shows the model used for noise-based calculations
Spectral noise requirements
The requirements give a limit on the antenna-referred spectral noise density. At higher frequencies, this limit is constant, but at lower frequencies, this limit increases. The increment follows a $1/f^2$ characteristic. The frequency at which the frequency independent characteristic takes over from the frequency dependent characteristic is at: $$f_{\ell} = 200 [kHz]$$ This frequency is the corner frequency of the noise and is located at the point where the 1/f noise equals the floor noise.
Optimal noise performance
Since the input stage is driven from a capacitive voltage source, there is an optimum in noise performance. This optimum is found when the input capacitance of the stage $c_{iss}$ equals the source capacitance $C_s$. In this case, the source capacitance equals: $C_s = C_A + C_F$. Since $C_F = C_A \ell$, $C_s = C_A (1+\ell)$ and therefore the optimum is found when $$c_{iss} = C_A (1+\ell)$$
Testing for feasibility
Since there is an optimum in noise performance, a test can be done if the optimal design in terms of noise is still within the scope of the requirements. If this is the case, the design can continue and tweaks can be made to this first stage.
After evaluating the expressions, the following design equation has to be valid for the stage to fall within noise requirements: $$\dfrac{3\cdot f_{\ell} \cdot C_s \cdot S_{v,floor}}{8 \cdot KF} > 1$$ Here, KF is a parameter that is defined by the technology of the transistor and $S_{v,floor}$ is the spectral density of the input-referred voltage noise of the active antenna. Like displayed in the section Design Overview, this noise floor equals:
\begin{equation} S_{floor}=6.25 \cdot 10^{-18}\,\left[ \mathrm{\frac{V^{2}}{Hz}}\right] \end{equation}Filling in the parameters gives:
\begin{equation} DesignMargin=23.44 \end{equation}