After determining the circuit performances in SLiCAP, a real implementation of the circuit has to be fabricated that can be simulated in programs like LTSpice. Correct biasing of the transistors is crucial for this step to ensure that the devices are in their correct operating regions. Some decisions have been made on how to bias the circuit:
The common-mode voltage of the amplifier is $900 mV$. Therefore, the input and output of each state should read $900 mV$ with 0 signal input.
Like determined, the common mode voltage of the amplifier should be $900 mV$. Therefore, voltage at the input and output can be set at this level. In addition, the drain current through the transistors should be $3.6 mA$, therefore a sinking current source can be added that sinks 2x the drain current ($7.2 mA$).
To complete the biasing, some logical deducions can be made. Since there should not be any output signal when there is no input signal, the gate voltage of M2 should equal the gate voltage of M1. In addition, the drain voltage of M1 should equal the drain voltage of M2. These voltages can be created by using voltage sources. Finally, the current needs to be divided equally between the two transistors. To force this division, a current souce at the output can be placed. This can be done because the input of the next stage has a high input impedance. The following image shows the biased input stage.
The biased output circuit has already been used in this project in Assignment 4 - Complementary-parallel CS output stage. The biased circuit was used to determine the operating points of the transistors, therefore this design can be used in the biased circuit as well.
The full circuit can now be implemented by using the biased input and output stages. One additional component is necessary, a resistor in the feedback loop. This resistor passes DC signal and feeds back the $900 mV$ from the output to the input of the amplifier, making sure that the common mode voltage is the same along the entire amplifier. In addition, to get rid of the common-mode voltage, a capacitor is placed in series before the output.
The next step is to find out if the circuit actually behaves like expected and to see where the behaviour differs from the SLiCAP simulation. The following figures display the performance of this first step of the biased amplifier.
The following graphs display the bode plots of the SLiCAP simulation with the LTSpice simulation on top. Both traces are very similar and only at high frequencies, the simulations differ a little bit. At low frequencies, the LTSpice phase deviates a bit from the 180 degrees, unlike the SLiCAP simulation. The reason is that a capacitor is added at the output of the amplifier, causing an extra pole at low frequencies. If the value of the capacitor is decreased, this effect is enlarged and a drop in gain is visible as well.
The noise behaviour of the amplifier is more than adequate. At $10 kHz$, the noise requirement is $100 nV/mHz^{1/2}$. In this case, it is $22.5 nV/mHz^{1/2}$. At $100 kHz$, the requirements are $10 nV/mHz^{1/2}$. The amplifier is at $5 nV/mHz^{1/2}$. In addition, the requirement for noise floor of $5 nV/mHz^{1/2}$ is also met. This means that there is still some room left for the rest of the biasing steps.
The amplifier should be able to drive at least $316 mV$. By applying an input voltage that is too high, the maximum drive capability can be identified at the output. From this figure, it is clear that the amplifier is able to drive around $400 mV$, which is enough.
The weak nonlinearity is tested by applying 2 input signals, one at $10 MHz$ and one at $12 MHz$. The amplitude of both of the signals are half of the maximum input amplitude. The simulation is ran for $1600 ns$ and the maximum timestep is $1 ns$. The peaks of these signals have an amplitude of $-25 dB$, while the steady portion of the figure has an amplitude of $-76 dB$, which is slightly bigger than the necessary $50 dB$.
Go to Assignment-6---Biasing_index
SLiCAP: Symbolic Linear Circuit Analysis Program, Version 1.0 © 2009-2021 SLiCAP development team
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Last project update: 2022-01-13 18:09:51